Joseph L. Larabell19672 Stevens Creek Blvd #206
Cupertino, CA 95014
Project lead for Verilog-to-Ikos model generation program. Responsible for specifying, designing, coding, and testing program, as well as handling field support issues. Later promoted to manage development team for automated ASIC/IP model generation utilities.
Responsible for simulation library generation, memory modelling, pre-sales benchmarking, and customer support for Ikos sales group (for Ikos VHDL and Verilog-based hardware accelerator). Also act as liason between other engineers in Ikos group and Ikos Headquarters in Cupertino. Have also written various utility programs as needed within EDA Division.
Contact: Mr. Akira Saito, EDA Sales Department Manager
Supported existing CAE customers in Japan after company announced end-of-life for CAE product line. Also managed migration of CAE customer base to alternate vendor's products. Assumed technical responsibility for the "High-Performance Engineering" features of the Redac CAD Expert toolset and for the new Design Adviser product. Became primary technical contact for most of the interaction with our home office in Tewkesbury, UK, including verification and reporting of software defects and assisting other engineers in getting technical questions answered by the development departments in Tewkesbury and Mahwah, NJ.
Contact: Mr. Hisao Shima, Vice-President and Manager of Operations
Continued support and enhancement of CGEN behavioral model compiler/translator developed at FutureNet. Ported Accugen (previously Acculib) model generation tools and ASIC database to UNIX environment. Developed enhancements to CADAT simulator and Accugen model generation tools to provide increased simulation accuracy for sub-micron ASIC libraries. Assisted in design of scheme to construct builder data files for SilcSyn synthesis tool from Accugen database. Developed translators to accept ASIC vendor data in various formats (including EDIF). Created method of producing truth-tables for Accugen libraries for use with Intelligen product. Headed design of second-generation ASIC database schema, structural/behavioral model compiler, and library generation scheme. Integrated timing-calculation algorithm from second-generation design into existing CADAT environment to satisfy immediate customer requirement for accurate sub-micron simulation. Developed dialogs and underlying code for Accugen user utilities under Vision GUI sub-system. Supported library development group as needed to satisfy vendor- specific modelling requirements. Prepared and delivered numerous presentations and training courses on Accugen to customers, vendors, Application Engineers, etc.
Contact: Rob Goldstein, Software Development Manager
Responsible for developing behavioral simulation models in "C" for complex logic devices. Designed and coded a compiler/translator (CGEN) which converts a truth-table description of a device into the necessary "C" code behavioral model to simulate the device. Ported portions of CADAT code to Fairchild Clipper (RISC) co-processor running in an IBM-PC environment. Designed Acculib model generation scheme and associated tools for automated production of vendor-specific simulation libraries. Wrote many miscellaneous tools and modules for product stress-testing and for use by other programmers in department.
Contact: Dan Robinson, Software Development Manager
Designed and implemented a test-interface scripting language for production test and field fault isolation. Supported real-time IBM-PC based debugger used in development of MIL-1750 computer. Wrote interface between existing hardware debug package and a logic analyzer. Designed and coded a screen handling package to consolidate and speed-up screen access for debugger software.
Contact: Terry Mrowiek, Software Manager
Assumed responsibility for file management software to run Winchester disk sub-system. Debugged drivers and utilities for Winchester disk. Designed duplex scheme and related drivers to allow redundant processors to exchange files. Developed PCM codec simulator to generate system tones. Supported hardware/software integration for in-house developed 80286 processor card.
Contact: Ben Barber, Software Project Manager
Assisted on firmware upgrade/speedups on existing voice/data PBX matrix. Designed interface to multiplex 32 voice/data PBX ports onto fiber optic channel to provide expansion of PBX beyond designed line capacity. Designed redundancy controller to allow remote system operation from central location (wrote firmware to drive 8049 uP on card). Worked with system architecture group to specify future product direction.
Contact: William Greason, Director of Hardware
Developed "Sidekick-like" desktop utility program for bundling with IBM-PC clones.
Designed inexpensive low-speed network for IBM-PC. Wrote Z80 firmware for IBM plug-in card, network controller, and communication server. Specified and started "C" language utility program for mail and file access. Wrote hardware simulator module to allow concurrent hardware/software development. Directed staff of two programmers working on network utilities and file server software. Designed and coded "C" language utility program for dual line telephone card which converts an IBM-PC to an executive workstation.
Contact: Mike Campion, President, C-Lan Technologies, Inc.
Designed memory controller for high speed multiported minicomputer memory, including priority logic for 14 ports, refresh controller, Hamming code ECC, and on-board control and diagnostic microprocessor. Defined control command set and wrote firmware to control memory configuration, execute commands, operate dual SDLC communication ports, and diagnose hardware. Designed hardware and software for SDLC adapter for a Compucolor microcomputer used in system integration. Wrote specification document for memory interface. Later became technical leader of multiport memory project.
Contact: Bob Propp, Manager, Computers and Networks Dept.
Designed memory and I/O board for NAVSTAR receiver. Compiled standard parts list and derated electrical specification document for use by engineers on project.
Contact: Richard O'Connor, Digital Design Manager
Wrote diagnostic programs for F15 signal processor. Wrote test patterns for HP2100 TESTAIDS system for board-level testing. Designed built-in test controller utilizing a Z80 microprocessor for a hardwired pre-processor system. Designed a data switch to coordinate data transfers among various computers and peripherals on airborne radar platform.
Contact: Doug Benedict, Section Head
B.S. Electrical and Computer Engineering, June 1978
Wayne State University, Detroit, Michigan
Grade Point Average: 3.35/4.00
DOB: 2 March 1956 (Age: 42)
Willing to travel/relocate
References available on request
Last content update: 27 May 1998
This resume is also available as a plain-text file
|Press the button on the right to be notified of changes to this page.|
[ HOME PAGE | FAVORITE PLACES | PERSONAL RESUME | GUESTBOOK ]